This invention relates generally to non-volatile semiconductor memories of the flash EEPROM (Electrically Erasable and Programmable Read Only Memory) type, their formation, structure and use, and specifically to methods of making NAND memory cell arrays and associated peripheral circuits.
There are many commercially successful non-volatile memory products being used today, particularly in the form of small form factor cards, which use an array of flash EEPROM cells. An example of a flash memory system is shown in FIG. 1, in which a memory cell array 1 is formed on a memory chip 12, along with various peripheral circuits such as column control circuits 2, row control circuits 3, data input/output circuits 6, etc.
One popular flash EEPROM architecture utilizes a NAND array, wherein a large number of strings of memory cells are connected through one or more select transistors between individual bit lines and a reference potential. A portion of such an array is shown in plan view in FIG. 2A. BL0-BL4 represent diffused bit line connections to global vertical metal bit lines (not shown). Although four floating gate memory cells are shown in each string, the individual strings typically include 16, 32 or more memory cell charge storage elements, such as floating gates, in a column. Control gate (word) lines labeled WL0-WL3 and string selection lines DSL and SSL extend across multiple strings. Control gate lines and string select lines are formed of polysilicon (polysilicon layer 2, or “poly 2,” labeled P2 in FIG. 2B, a cross-section along line A-A of FIG. 2A). Floating gates are also formed of polysilicon (polysilicon layer 1, or “poly 1,” labeled P1). The control gate lines are typically formed over the floating gates as a self-aligned stack, and are capacitively coupled with each other through an intermediate dielectric layer 19 (also referred to as “inter-poly dielectric” or “IPD”) as shown in FIG. 2B. This capacitive coupling between the floating gate and the control gate allows the voltage of the floating gate to be raised by increasing the voltage on the control gate coupled thereto. An individual cell within a column is read and verified during programming by causing the remaining cells in the string to be turned on hard by placing a relatively high voltage on their respective word lines and by placing a relatively lower voltage on the one selected word line so that the current flowing through each string is primarily dependent only upon the level of charge stored in the addressed cell below the selected word line. That current typically is sensed for a large number of strings in parallel, thereby to read charge level states along a row of floating gates in parallel. Examples of NAND memory cell array architectures and their operation are found in U.S. Pat. Nos. 5,570,315, 5,774,397, 6,046,935, and 7,951,669.
Peripheral circuits are formed on the same chip as the memory cells but they have very different functions that require different device structures. Thus, a process that is suitable for forming a memory array may not be suitable for forming peripheral circuits and vice versa. While it may be possible to mask the memory array to perform process steps that affect only peripheral circuits and mask peripheral circuits to perform process steps that affect only the memory array, this increases the number of process steps to manufacture a memory chip. In general, the cost of manufacturing a memory chip increases with the number of processing steps used, and the number of defective units tends to increase also. So it is desirable to use the same process steps for the memory array and peripheral circuits.
Thus, there is a need for a memory chip manufacturing process that forms the memory cells and peripheral circuits in an efficient manner and there is a need for structures that can be formed accordingly.